The present invention relates to integrated circuits and, more specifically, to an improved chip-to-carrier attachment method. A prime objective of this invention is to furnish high-density multi-chip assemblies with superior reliability.
Integrated circuits are used in most all categories of technological products embracing both commercial and military applications. Implementation of the advanced technology segment in this product spectrum requires both high-density and high-performance systems. Their realization necessitates high-density integrated circuit chips and a compact packaging technology.
Chip circuit density is afforded by advanced integrated circuit process technology, whereas compact packaging is achieved by multi-chip assemblies. While multi-chip carriers have been fabricated using various technologies, the highest chip density has been attained by fabricating carriers with the same process technology used to make the chips. The resulting density substantially exceeds that obtained with printed circuit boards carrying single chip packages.
Improved density provided by a multi-chip carrier environment results in shorter interconnection lengths between adjacent chips and, therefore, better performance. On the other hand, the size of single chip packages, which limits chip placement density, is characterized by longer interconnections and thereby poorer performance.
Furthermore, multi-chip assemblies provide for combining generic technologies such as analog, digital, bipolar and CMOS instead of using the more costly mixed technology chips, e.g., Analog/Digital and BiCMOS. For example, a multi-chip package using separate digital and analog chips combines simpler technologies with better individual yields. This results in highly functional cost-effective systems.
Among the chip mounting techniques the "flip-chip" method provides superior functional density since signal and power interfacing is no longer limited to the periphery of the chip. System density is further increased by accommodation of active circuits on the multi-chip carrier.
"Flip-chip" mounting involves turning the chips upside down for direct attachment to the opposing multi-chip carrier. The final assembly requires a reliable attachment method as well as precise alignment of the components. A conventional attachment technique joins opposing contact areas using solder bumps. The relatively new self-alignment technique, which is discussed in U.S. patent application Ser. No. 295,729, uses pin blocks which mate with chip slots and carrier apertures. It allows for precise, convenient and repeatable alignment which facilitates assembly and testing.
Testing of multi-chip assemblies is of equal importance to reliable attachment and alignment methods. A test assembly, using test bumps in place of solder joints to connect chips and carrier, can be either interfaced with a tester or serve as a "system-emulator". The latter concept was introduced as "substitution testing" in the above patent application. This "in-system" test environment has a significant advantage over conventional test set-ups, by accurately representing the multi-chip system and thereby avoiding the need for vector testing, transmission line driving and ESD circuits, etc. In addition it features simplicity and efficiency. Furthermore, the substantial costs of test development and associated hardware, which rapidly increase for testing of more complex systems, are also saved.
Solder bumps incur a reliability problem due to the shear strain produced by differential thermal expansion between chips and carrier. This is caused either by a material mismatch or simply a temperature difference between assembly components made of the same materials. Results of solder bump reliability studies have been reported by Ernest Levine and J. Ordonez in "Analysis of Thermal Cycle Fatigue Damage in Microsocket Solder Joints", IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-4, No. 4, December 1981, pp. 515-519; and by Fumio Nakano, Tasao Soga and Shigeo Amagi, Hitachi Research Laboratory-Hitachi Ltd. Hitachi, Ibaraki 319-12 Japan, in "Resin-Insertion Effect on Thermal Cycle Resistivity of Flip-Chip Mounted LSI Devices", ISHM '87 Proceedings, pp. 536.
More recently, these studies have been extended to low temperature operation and their results reported by Ho-Ming Tong et al. in "Ceramic Packages for Liquid-Nitrogen Operation", IEEE Transactions on Electron Devices, Vol. ED-36 No. 8, August 1989, pp. 1521-27. Solder joints develop fatigue during temperature cycling until failures occur. Their use is thus subject to deterioration and limited lifetime.
Failure of solder joints in flip-chip assemblies gave the impetus to look for alternative chip-to-carrier attachment methods. One such method proposes gold bumps as chip terminals contacting gold pads attached to flexible membranes on the carrier. Under differential thermal expansion between chip and carrier, the bumps are free to move due to the flexibility of the membranes. This approach avoids the rigidity of permanent solder bump joints. It also assures electrical contact of all mating pairs despite lack of parallelism in opposing surfaces of chip and carrier. This is accomplished since the resulting differential spacings between mating contact pairs are compensated by differential depressions of corresponding membranes through application of pressure during assembly.
The gold bump attachment method features high connection density, chip demountability, substitution testing and remains reliable during differential thermal expansion. Here the gold bumps can be made reasonably small since the carrier uses a single layer metal system. However, if a multi-layer metal system is employed the overall size of the gold bumps is increased to enable them to clear the upper interconnection layers when reaching down to the membranes and maintain sturdiness at the same time. The resulting lower connection density, uneven chip surface, as well as the fact that gold is an unconventional metallization for mass produced integrated circuits makes this attachment method less attractive for very large scale integration (VLSI) circuits.
It follows then that a different attachment method for multichip assemblies is needed which is applicable to VLSI circuits using multi-layer metal structures. The attachment method should furnish a reliable interface which is maintained during differential thermal expansion. Preferably the attachment structure should be fabricated employing conventional IC processing techniques used for chips and carrier.